Decade counter for producing an output at the count of nine



Feb. 25, 1958 J. o. PAIVINEN 2,824,961

DECADE CQUNTER FOR PRODUCING AN OUTPUT AT THE coum 0F NINE 2 Sheets-Sheet 1 Filed March 4, 1955 7 INPUT 6| SOURCE R SIGNALS 53 TIMING PULSE 50 SOURCE 38 J L o ,se DELAY 84 -82 TIMING 2 v PULSE 4O +14 VOLTS SOURCEL52 INVEN TOR. JOHN O. PAIVINEN mac/2344 1 AGENT Feb. 25, 1958 J. o. PAIVINEN DECADE COUNTER FOR PRODUCING AN OUTPUT AT THE COUNT OF NINE Filed March 4, 1955 2 Sheets-Sheet 2 ifiqgfi'i Rm v INVENTOR. JOHN O. PA'IVINEN AGEN'T m 6N I HWHI-IBE.I-IL $347? 0 3 5.6 6 3 NQ LEEE U 2,824,951 Patented Feb 25; $58

DECADE COUNTERFOR PRGDUCING 'AN OUTPUT AT- THE COUNT OF NINE John O. Paivinen, Berwyn, Pa., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Application March 4, 1955, Serial No. 492,202

3 Claims. (Cl. 259-27) This invention' relates to' counting devices and more particularly to electronicdecade counters which utilize a series of binary coupled flip-flop stages.

Methods have previously been employed for converting a binary counter to a decade counter. Such methods have required the triggering of'one flip-flop stage from another.

This'has been accomplished by inter-stage networksiwhich An object of the invention is to provide improved means I output signal in response to transition from one state to another.

According to .the inventiona decade counter is comprised o-f four binary coupled flip-flop stages which may be coupled forcounting in response to a source of signal pulses. A counter output circuit is coupled to and coincidently. controlled by the first and fourth flip-flop stages to provide output signals indicative of the count ofnine. lncluded in the coupling between the first and second stages is an inhibit circuit coupled to and controlledby the counter output circuit for preventing a change of state of the secondfiip-fiop stage from signals occurring during transition-of the first stage when the counter indicates a count of nine. Finally, a clearing circuit is coupled to and under the coincident control of both input pulses from the source of signals to be counted and signals developed at the counter output circuit and operates to clear the fourth stage in response to the tenth signal to be counted, to thereby automatically reset the counter with the'tenth input pulse.

Other objects and advantages will become apparent Thecounter of: the invention'comprises a fourstage binary counter which is modified to yield a decade count. This .modificationiis accomplished by the utilization of gating circuits'to interrupt thebinary cycle at binarynine and to resetthei'counter" to" binaryjzero' in response to the tenth input signal to becounted:

Referringmow to the logicaldiagram of the" counter illustrated'in Fig; 1, the counter is comprised of the four binary connected bi-stablefiip-fi'ops 21 22 23 and 24 representing the binary counting stages 1, 2, 4, and8, respectively, as indicated by the subscriptsaccompanying each of the reference characters. Each flip-flop is controlled by a single input conductor towhich positive pulses arev applied in order to complement the state-of the flipfiop; that is, to causeth'e flip-flop to switch from its resident state to the opposite state. Each of the flip-flops 21 22 and 23 produces a positive outputpulse upon th'e corresponding output-conductor 31, 32, and 33' When'the respective flip-flops are switched from the on 01"1 state to the off or TO state. his to be specially noted'that the output signals produced upon the conductors 31, 32, and 33 when their'associated fiipafiopsare switched from 1 to 0 are pulse'outputs and not merely'a change in DI-C.= potentialrlevel. The output conductor 32 of the secondfiip+fiop=stage22 is connected to the complementinginput conductor.47-of the third flip-flop stage 234, and in turn output conductor 33 of the third flip-flop stage 23 'isconnected to'. the complementing input conductor of theifourthflip-flop 24 Every time thesecond flipflop 22 switches from the l to the 0state, it'transmitsa positive pulse to'the complementing input of the thirdfiip-fiop-23 -=to effect switching of the latter. Similarly, each time the z third fiipafiop 23 switches irom--the 1 to-the-- 0- state,*,switching*ofrthe fourth flip-1101124 is effected.-

interposed between the output conductor 31 ofithe first fiip-fiopjistagefll and the complementing inputconductor .47. of the secondafiip-flop stage 22 is an inhibit gate 46. The-gate. 46. is inhibited by the 'potentials applied: toits second input-conductor 48 by. pulse amplifier 41 which comprises the. output-circuit. for the decade counter. The inhibit .gatefi: depends for its operation upon zthevinterr action .of opposing, signals from .the first fiip-flop stage and the .pu1se.amplifier.41. Normally the. potential. upon conductor 48 is a D..-C. potentialwhich permits the passage of the positive-going pulse from .the first fiip-vfiop to..the second flip-flop tov accomplishtswitching of the latter. However, as .will be shown hereinafter, when .the-counter reaches the count of nine and in response-.to. the application .of the followingtiming pulse, the pulse amplifier 41 functions toapply a negative pulse to the input conductor 48 of gateAfi coincidently with the transmission by the first'filprrlop 21 of the positive pulse on conductor 31 to theinhioit gate 46. By buckingthe negative pulse againstthe positive-pulsethe positivepulse is'canceled wnereby'th'e potential of the. complementing input conductor 47 is .prevented from becoming positive; and switchin'g'of'the second flip-flop inresponse to a signal from tne'first flip-flop is prevented.

The'firstand fourth flip:fiop stages have further output conductors 36 and 37, respectively, which assume one or the other of two D.-C. potential levels in 'accordance'with the state of the fiip-fiop and. which provide a source of D.-C. control potentials for gating signals at'output gate 35, which 15 described hereinafter in greater detail.

The input circuit for the decade counter comprises the coincidence gate 59 to which are applied both information signals from a source'of input signals 51 and periodic clock pulse signals from a clock pulse source"52. The

clock pulses establish the basic counting rate'of the counter and are positive-going, narrow pulses; The information pulses comprise interspersed binary one and binary zero signals'which are synchronized with the clock pulses and of which it is desired tocount' only the binary one signals. In response to the coincident application 'Of a'binary one signal and' a clock pulse, input gate 59 applies-a positive pulse toconductor 5310 complement the first fiip-flop'zl' However, =-the--coincident appli'catiom'of"a binary zero sig nal andaclock pulse to the no output pulse therefrom.

coincidence gate 50 produces It is the function of coincidence gate 55 to efiect resetting of the fourth flip-flopstage 24 to the state in response to the tenth input signal to be counted; Accordingly the conductor 54 Supplies the coincidence gate 55 wlth signals to be counted from the input coincidence gate'SOL The coincidence gate SS isfurther connected by a conductor 56-to the pulse amplifier 41 which, as will be shown hereinafter, conditions the gate 55'to either pass or-inhibit the signals to be-counted in accordance with the count attained by the counter., The coincidence gate 55 is connected by conductor 59 and or? gate 57 to the reset input conductor 58iof thefourth flip-flop stage" r 24 Only when the counterreaches.the count of nine .does the pulse amplifier 41..apply:a. positive pulse to the 7 input conductor; 56 of the coincidence gate 55 coincidently .with the application ,of .the'signal ..toibe counted to the other input conductor .54 ofthe coincidence gate 55'.

This positive pulse conditions the gate S'to pass a positive signalvia conductor 59 and ?or'. gate 57 tothe-reset 'conductor 53 of the fourth fiip-fiop24 to effectreset'ting ofthelflip-fiop' 24 to its 0 state; ,Or r gate. 57 may 7 beany circuit capable of passing a positive pulse applied to either'ofitsinputs 59 or65. I a

.The normally cut-ofi pulse amplifier 4l which' comprises th'e-output circuit for the counter is conditioned for conduction in accordance with the states of the first and fourthfiip-flOp stages 21 and 24 and is tri gered bye-clock pulse from source.52-if properly conditioned.

' Accordingly, 'a coincidencegate 35'contro'lled by -con: 1 ductors 36 and 37 from the respective flip-flops 21.7 am 24 -isconnected by a delay circuit 39- to the 'pulse amplifier-41. A'conductor 40 connects the pulse, amplifier ll-with the source of clock pulses 52. whenjthe count reaches nine'both of the flip-flops; 21 and 24 are in the If state. The c'oincidencefi gate 35 in-response to 'the' state transmits a pulse to flip-flop stage 22 to set the latter to the 1 state. In response to the third input signal to be counted, fiip-flgp stage 21 is set to the 1 state. Thus both flip-flop stages 21 and '22 are in the 1 state to indicate a count of three. The fourthfsignalj to be counted effects resetting of the first flip-flop stage 21 which in switching to theT)? state .transmitsa signal to the second flip-flop stage 22 to reset the; latter to the V 0 state, and in turn the second flip-flop stage 22' iwhen.

switched to the 0, .statetra'nsmitsfa signal to the third W in tu rn triggersthesecond'flip-flop to the l state. Hence it is seen that a'six1is represented .by flip-flop stages 22;.

and 23 being in'the 1 state'and'the. remaining flip-flop stages being in' the "0'7; state: The seventh input'signal to 'be counted-iadds the first iiip-flopstage 21 to the flipflop stages 22- sand 23 which 'are already. inthe ,lf

state. In response to theeighth inputsignal all' of lthe f flip-flop stages 215,22 and 23 iare.switched to the 0 state; and as "the flip flop stage 23 iswitches to the "0 state it'tr ansmits a complemental'signal to. thefourth flip-flop stage 24 to switchit to the 1 state; LTo repre V sent nine the {first flipflop stage 21 -is switchedto the Q counted.- Hencea nine, as stated hereinabove isreprc I sented by flip-fiop stages Z b-and 24g-fassurning the. flf

state and the'other'sta'g's assuming the 0 state. Through,

and-including the count or nine, the operation of the.

co'unt'eris pure binary; however, in order for the counter f to operate as decadefcounter, it isjnecessary that itbe coincident setting of thefiip-fiops 21 and 245m the 1' state applies-a conditioning potential through thedelay cir'cuit39 tothe'lpulse amplifier 41 in order to condition the; latter to be. triggered by the succeeding'clock'pulse. The delay circuit insures that the pulse amplifier 41 is not conditioned in time tobe triggered by the same clock pulse which sets the counter .to the nine count.

When the pulse amplifier 'istriggered on, a negative inhibiting pulse is-applied to conductor 48 and a positive pulse is applied to conductor .56 to. condition thefrespecinput conductorSS toswitch' the first 0'state; and because the gate 46 is inhibited the signal;

21 when it is reset-does not switch the second'flip -flop 22 fwhich is already in the "0 1 state. Further. the tenth'input signal also efiects applii cation of a complementing signal .bvmeans'of conduc-x torf54, fand. gate 551and for? gate 57 to the fourth flip 1 flop stage 24 'to'resetit to thefO-state.f;Hence,;as inttive gates46 and 55 to inhibit and pass their signals.

7 'In'order to arbitrarily presetthe counter to any count the flip-flop stages 21 ,22 23 and 24 are provided with the preset inputfconductors 61, 62, 63, and 64,re-- f spectiviely." A positive signal applied to one of thepreset conductors sets the associated flip-flop state, not already in the 1 state. '7

stage to its 7 I i In order to clear the'counter, that is, set it to zero count,

@a-clear conductor 65 is commonly connected to the 0' state 1side;of*each of 'the flip-flop stages .21 22 and 23 and through-"o'ri gate :57jt'o 'the 0 state side of flip-flop stage 24 Clearing of the counter is accom plished by the application of a positive clear signal to 'all stages simultaneouslywherebyall of the In order to demonstrate the mannerin which the 4 decade counter operatesga en rate eounter. cycle will 'bedescribed with referenee to the chart of Fig. 3. 7

transmitted byjfirst flip-flop .1 state inl response to the fninth input signal 'to 'be reset to zero in response to the tenth input'signaltqbei:

counted. I 7

The counter is conditioned; to accomplish this'resetto fzero by the switchingoframplifiercircuit 41to its on condition in response to-the timing pulse following the .ninth input pulse'whereby' gate 46 becomes inhibitedfand :gate passes a signal with'the applicationof the'tenth. input pulse. Accordingly, in response to'the'tenth'input signal to be counted, a complementing signal is appliedto dieated by the chartof Fig; 4, aftercounting'the tenth Assume first that theelear circuit hasi'been operated .whereby all of the flip-fiop stages 21 22 ,23 and 24' fcept whenthe count reachesinine; The first signal to be' 7 are in the OTstate, and the eonnter stands at zeroeount; Initially, gate 46 is uninhibited and gate 55 has no coincidentsignal sr; These gates remain in this condition ex;

The second signal tol circuit will now signal allfour,flip-flopIstagesassume the "0 state, and

' the 'cou'nter isjre'set to its'ifiitial condition. An output 1 signal is presented by pulse amplif erfil onlyjwhe'n the.

count reaches nine."

Having described tainfnie sarnef ref erence l characters Ia's in Fig. ;1.v

' 1 01 and 102 which have their anodes connected, through resistors .103 and 104:to a. potential source. .01? 1+2l01 The control grid response. to it the counter and its operation in terms 'of thelogical diagramfa preferred embodimentof the 4 be'described in detail withrefe'rence' to i Fig.1. Forconvenience likeicornponents fFig. 2"re; 7

101iand1 st Additionally,

' shunting capacitors 98 and ,99 tare provided ,for there; triodes "1 01 7 and 102 are als c nn'ected through the r r sistancis' 109 d .29'l ii lii fil i l f -(5 Pq in .5

:pulse potential.

source of 1225 -volts. An output conductor-.36 is .pro-

jected from the cathode of triode l01, ,and the cathode is further connected to the terminal lllthrougharesistor 112 by-passed. by a capacitor 113 to thusproducean output D.-C. level indicative of.thefiip-flop-state. In order to limit the D.-C. potentials assumed by the output line 36, output line 36 is clamped by diode 114 to a maximum potential of +14 volts with triode lolconducting. and by the diodes 115 and 117 of and gate 35 to a minimum po-' 'tential of ground with triode 101 cut off. The cathode of triode 102 is connected througha choke coil 12%? to ground, and the output conductor31'isprojected from -the cathode. A damping resistor'121' anddiode 122 are serially connectedfrom groundto the output conductor '31'and shunt the choke coil 120. The choke coil 120 'comprises a resonant circuit which produces va sharp,

positive-going output pulse of approximately "30 volts upon the output conductor 31 when the triode'1'02 be- --comes conducting. The damping resistor 121 and diode 122 function. to prevent ringing and thereby permit only the single sharp, positive pulse 140*tobe produced .upon

output conductor 31 when the triode 102 switcheson.

The set or 1 state of the-flip-fiop 21 fis defined as .the condition under which triode 101 conducts and-triiode 102 is cut 013?, to thus produce a high D.-C. level at lead 36. 'The reset or 'state of the flip-flop '2l is defined by the opposite conductivestates wherein triode "Jim-conducts and triode 101 is cut-oft, and thus a pulse 114tlisproduced during transition to state 0 at' lead "31. In'order'to efiect switching of the-fiip flop,=the-input conductor 53 is connected through 'dio'des 123 and 124 .to the. control grid ofthetriode l0l-and through'diodes .125 and 126 to the control gridofthe triode102. The

diodes 123, 124,1125, and 126 are-:so oriented that a positive pulse on input conductor 53, for example, apulse a-whichraises the conductor 53 to zero volts, ispassed-to the control grid of the non-conducting'triode .whose control grid potential is negative with respect to the positive However, the positive pulse-on input conductor 53 is blocked from the grid of the conducting triode whose control grid potential is positive :with', respect tothepositive pulse potential'because of theintermediate .-:diodes.124 and 126. Thus'the positiveinput signalsare .always applied to the control grid of the non-conducting ,triodeand effect switching of the flip-flopto produce the .complement of the state of the flip-flop at'the timethe input signal is applied.

In order to preset the flip-flop .21 to its set,'or l"'state, an input conductor 61 is connectedthrough-a:diode 12$ to the junction of the diodes 123 and .124. Assuming triodelfiZ to be conducting and triode 101 to ;be cut1ofi, the applicationof apositive pulse to the input conductor lfinds the diodes 128 and 124 properly oriented so that the lpositive pulse reaches the controljgrid of the triode ,101 and causes itto conduct, whereupon the flip-flop assumes its 1 state. In order to. clear, or reset, thej flip- ,fiop .121 an input conductor '65 is connected through a diode 129 to the junctureof'the diodes-125 and-126.

Finally, in order to limit the negative potential swing .of:the control gridsofthe triodes 101 and 102, the input lead 53 is clamped by diode.130 to a l2 volt source. By limiting the extreme to which the grid of the non- ,conductingtriodegoes negative, less time is required to .raise the grid of said triode to a conducting potential. Thereby ashorter response time and faster switching of the flip-flop is obtained. Without this clamping means the grid of thenon-conducting triode assumes a negative potential of'-30 volts or thereabouts. The diodes 124 and 1216 can be omitted,if desired, but they are useful in reducing the loading imposed upon the flip-flop by the parallel back-resistances of the other'diodes.

In order to give a visual'indication when theflip-fiop 21 is in the 1 state, a neon lamp and'a' resistor are'con- --nected=in-seriesacross the anode resistor'103 cjf'triO'del'Ol.

-is more than sufiicient to ignite the neon lamp. 'With triode 101 cut oft" there is no potential drop across the anode resistor andthe neon lamp remains off.

Because the other three flip-flop stages 22;, 23 and 24 are quitesimilar to the flip-flop. stage .21 only the manner in which they differ from flip-flop 21 will be described.

Theoutput conductor 31 of the flip-flop stage '21 is coupled to the input conductor 47 of flip-flop 22 by a capacitor, 131. A resistor 132 connects conductor 47 'to a potehtial source of 225 volts. Flip-flop 22 differs from flip-flop 21 in that no useful output signal is necessary from the left hand triode 135, which conducts when 'the'flip-fiop is in the "1 state. Accordingly, the cathode of triode 135 is connected directly to ground. As in the case of flip-flop 21 a clear input conductor 65 is provided to reset'the flip-flop 22 to the "0 state, and a preset conductor 62 is provided to setthe flip-flop 22 to the T state.

"Each time that the first flip-flop 21 switches from the -1'to the zero state a positive-going pulse of approximately 30 volts is transmitted through capacitor '131 to the input conductor 47 of the second flip-flop stage'22 '-In-responseto the application of the positive-going pulse, "the potential of input conductor 47 starts upward from its clamped potential of l2 volts and as soon asthe 'grid-of the non-conducting triode is sufiiciently positive, the non-conducting triode startsto conduct and the flipfiop switches to the opposite state.

The circuit constants are so chosen that the flip-flop 22 can actually change the charge on capacitor 131 and'thus drive conductor 47 downto the clamped potential of l2 volts. =manner the waveformof the pulse appliedto conductor In: this 47-.is choppedshort asindicated by the waveforms 140 and 141 and cannot cause spurious double triggering'of :thefiip-flop 22 The circuit parameters of;the other flipfiops arealsochosen with this type of operation inmind.

In order ,toinhibit the transfer of -a;switching signal .st-age22 in-response to the. tenthiinputsignal torbe count- Normally the; pulse amplifier However, in response to the application to the counter ofithe timing pulse following'the ninth input signal, the potential of the conductor '48 and the cathode ofithe diode'137 is pulled down to a potential of l2-volts by a.negative pulse from the pulse amplifier-41 coincidently with the transmission of the positive pulse from the first flip-flop 21 upon the conductor 31. With the cathode of diode 137 at l2 volts, the diode conducts and applies the negative volt pulse to one side ofthe capacitor 131 at the same time the positive pulseis applied to the opposite side, and the negative pulse holds the inputconductor 47 of the second flip-flop sufficiently negativeto prevent switching of the flip-flop.

The output conductor 32 which is projected 'frorn'the cathode of the right hand triode 136 ofthe secondflipflop stage 22 also comprises the complementing input conductor to the third fiip-flop'stage 23 A capacitor 142 is inserted in the conductor '32 and a resistor 1'44 connects the third flip-flop 23.; side of'the capacitorto a source of 225 volts. The third flip-flop 23 is'identical to the second flip-flop 22 A clear input conductor 65 and a preset conductor 63 are provided and operate in the same manner .as the clear and present conductors 65 and 61 for the first flip-flop 21 Similarly, the output conductor 33 of the third'flipdiop stage 23 also comprisesthe input conductor-for flop-flop 24 and includes a capacitor 145. 'A-resistor 146 connects the flip-110 24 side of thecapacitorto asource of 225 volts. The fourth flip'f'flop' 24 -"diifers from the fir'st flipfiep only in that no useful pulse output isnecessary at the cathode of the right hand triode 148 which conducts when thefiip-fiop is in the T state;

"'p'ut conductor 37.1is projected'tromthe grid of the left. hand t'riodej1l47jintthesame manner alsnoutput conductor 36, of the first flip-flop stage 21 With flip-11013 24 rea zero volt potential.

. 1 .The timing pulse source 52 maybe any 7 i for example, the timing track andypulse generation ci rcuits of a magnetic drum storage system; 'Thi periodic trigger pnlses'which are sizpplied to the conductor 43 coincide in time with the cloc'k pulses and rise from'a quiescent level of zero volts to a +114 yolt lpotential. 5

i ,The delay circuit 39, exceptwhen the counter-stands .Qatithe count of nine, appliesa .zero volt D'.-C. potential However, the. outset to the state, the outputlconductor 37 assumes a i The fourth flip fiop tstage 2 43 input 64 1's provided to preset the flip-flop in thesame'manner j 'that preset input 6lfpre'sets the firststa'g'e 21 .11 Clearing of'the fourth flip-flop stage is accomplished by the i application of-a positive potential to the clear. input conductor 65 whichisconnected through diode160, conducftor 58 ,iand diode'159 to the -co n trol grid o f triode 148. As statedhereinabove andfgatefiS function s tocona 7 on its? cathod qdiode 83 conducts to place the zerolvoltl potential uponjthe input conductor 86 of the pentode and' V alsoiupon the anodeof diode 84. The +l4tvolt trigger Q pulses fi nd the diode. 84 non-conducting because its cath- Conversely, withjthe fiipflop 24 set to the .lfstate the output conductor. .37sass'umes a '+l4 volt pote'ntial.

delay circuitlw'applies a'-}.14 volt DC. potentialto 1 prises a pair 10f diodes 115 andj llqhaving their anodes connected through a resistor 118 to a source of 1+2l0 volts; and having theirgcathodes connected to the conductors-36 and 37,, respectivelyr The commonly con-' nected anodes of the diodes115 andg116 are also'conlnected'by diode 117 to groun'd. Finally-the and gate 7 output conductor 38 connects the commonly connected anodes to the delay'circuit 39. Whcn the counter reaches I the'count of nine,-both thefirst flip-flop stage 21 and .the fourth flip-flop stage 24 1are in the 1 state and 1 both conductors 36 and 37 apply a l4 volt .D.-C. level to the cathodes ;of diodes 115 and 116,-respectively, With the anodes of both diodes115 and 116 connected through 1 resistor. 118' to the +210'volt potential, both diodes 115 and 116 conduct equally to place the +14 volt potential upon the and? gate'outpn't conductor 38. "If only one i V of the flip-flop stages 21 and 24g is'tin the 1 "state,

one of the conductors 36' and 37 will be at a;+14 volt potentialand the other'asz ero'volt potentiaLfUnder these conditions, the diode with' the zero volt potential condiic ts and applies the zero volt potential to the output conductor 38.' Likewise with both flip-flop stages 21 and 24 -in the 0 state, the conductors 36 and 37 both .assuine zero volt potentials and both conduct to pa ss the zero volt potential to the andf gate output'conductor 38; The diode 117 functionsas a'clamping diode which prevents the triggering of one flip-flop stage from spuriously triggeringthe other flip-flop stage connected to'the gate. i

The, delay circuit 39 which is interposedibetwe enthe ode is more positivethankitsanode Therefore as long 7 as the. conductor "42 remains. at aliero" voltpotential, the conductor"86 remains at zero .voltsal'so; 'and the trigger' j ,pulses are,ineffective'to overcome-the cut-Joli bias of the 'pentodef95h However, "whe'nithe coonter stands'at a count of nine,

the cathode ofdiode 83. 1Withthe conductor Atlat'its inter-pulse levelof zero yolts, the diode 84 conducts and conductor 86 assumesIthei zero volt potential. 7 However when the trigger pulseraises the potential of the cathode otdiode 84 to l4 volts, both diodes 83and .84

are coincidently at +14; -volts, and 'b'oth conduct'toraise- I the potential of conductor; to'+l4 volts also. ln'r'e- Y sponse, pentode 95 conducts for the duration of the trigger pulse and energizesthe "primary 'winding;89-to induce oppositely polarized signalsfin the secondary windingsr90 and 91 of the transformerBS.

coincidence gate and the pulse-amplifier 41 may be i any suitabletype, for example, an LC delay circuit.

A preferred embodiment of the pulse'amplifier .41' is illustrated in Fig. 4. A pentode 95 has its. plate connecttransformer 88 and the upper end of the primary Winding is connected to a +210 volt source. The screen grid iis tconnected througha resistor; 85 to a suitable source of r positive potential, and the suppressor and cathode are .commonly'connected to a source'of +14 ivolts'to main tain the tube :norrnally cutoff; LA coincidence gate 82' 1 supplies triggering "potential .to 'th e 'control' grid of the pentode; Theroirieidenc'e gate 82 isconiprised of a pair of diodes 83'and 84 having their anodes commonly} connected to the conductor 86 and further connected by g a a resistor '85 to 'a source of +210yolts; The "cathode of thediode 83 is connected by lead42. to the delay circuit a 139 and. the cathode of diode 84 is connected by conductor tothe timing pulse sonrce52.

suitable source,

' tolthecathode of diode 83 With'a zero volt potential .75

'The secondary winding 90 is connected at'itslower'end to l2 volts and at its upper end to output conductor. 56, With pentode 95 non-conducting, conductor, 56-assu1nes the. 12..volt potential. However, whenthe pentodef9 5 1s pulsed to energize the transformer'a positive going sigf nal is induced in the secondary Winding 90 to' raise the conductor '56 to ,a-tpot'ential, of about zero voltsgjln' similar manner thejsecondary winding :91 is connected at its upper end-to gronndpo tentialand at its lower. end to output conductor 48; With pentode 95.cut ofl lconductor 4 8 displays the; ground potential: .However," when the] Y transformeris pplsed inlresporise tothe timing pulse'jfole r 1 lowing the ninth input signal, theconductor ASZis'driVcn-L more-negative thani.*12 volts.a Damping and'clampi'ngz i 7 means may be added .to'the secondary ,-.of*the transformer. if desired. l g

I The'input coincidencegateSO of a pair of diodes151 and 152 having their anodes oom monly connected to thecathode of a diode '53 whose anode is-connected through aresistor 154 t0 a sourceof +210 .volts. 7 The complementing input. conductor 53' for. the

first flip-1101521 is projected from the junction of the diode 153 with resistor 154. The cathode of diode 151 is supplied with the input signals to 'be counted and the cathode; v of diode 152 is supplied withperiodic clockapulses The f a clock pulses comprise narrow positive-going signals which V J ed to the lower end of the primary. winding 89 of a {a pair of diodes 15s and;

rise frorn'a'quiescent level of 12 volts toa potential of zero volts. The signals supplied'to the'diode 151 comprise interspersed zero and. -12 volt potentials 'synchro-' m'zed with the clock pulses and representing'binary one and binary zero, respectively, of! which ittis' desired to' count only thebinar'y one signals. 7 V

application of a zero-volt binary one signal and atzerovolt clock pulse to the coincident gate 50 raises the ,po-

' tential of-input conductor 53 to a zero-volt potential and zero signal hasno effect upon the flip-flop stage 215}? 0nd output c'onduct'o1154"which is projected from the commonly; connected .ahodesflojthe diodes 151- andf152" V windings 9o and91 Fig. 2 is Yet 5 Only the coincident Input'eoinc idenee'gate 50"is. also provided with a sec- 7 and "is connected torthe' cathode of "diode'155 of the fcoincidence gate-55. 'The coincidence gate comprises '156 havipgl;t 1f aned com? The cathodebf diode 156 is connectedby conductor46 to the output conductor 56 of amplifier circuit41.

In response tothe application of the tenth-signal to be counted,

:azerovolt signal is applied to diode 155 of coincidence gate 55; and simultaneously, the pulse amplifier 41 applies a zero volt potential to the diode 156 of the and gate 55 via the conductor 56. This simultaneous application of zero volt potentials to the cathodes of both diodes 155 and 156 causes both diodes to conduct to apply a zero volt potential to conductor 59 which applies the zero volt potential through diodes 158, conductor 58, and diode 159 to the grid of triode 148 to efiect conduction of the triode and resetting of flip-flop 24 to its state. With the counter standing at any count other than nine, amplifier circuit 41 applies a 12 volt potential via conductor 56 to the cathode of diode 156. In response to the application of the -12 volt potential, diode 156 conducts to apply the 12 volt potential both to the conductor 59 and to the anode of diode 155. With the --12 volt potential on the anode of diode 156, the zero volt signals from and gate 50 find diode 155 cut ofl and are unable to cause resetting of the fourth flip-flop 24 The diode 153 functions to prevent a malfunction of the counter. If the diode 153 were not present and in response to the tenth input signal to be counted the first flip-flop stage 21 were to trigger before the fourth flipfiop stage 24 the pulse at the commonly connected anodes of the diodes 151 and 152 would be chopped short. As a result the fourth flip-flop stage may not be triggered. This diode 153 prevents the first flip-flop from pulling down the potential at the anodes of diodes 151 and 152.

It is seen that diodes 158 and 160 having their cathodes commonly connected to conductor 58 comprise the equivalent of the logical or gate 57 of the logical diagram of Fig. 1. A zero volt potential applied to the anode of either diode 158 or 160 accomplishes clearing, or setting to 0, of the fourth flip-flop stage 24 Although the amplifier 41 has been illustrated as a pulse amplifier, an amplifier producing D.-C. potential outputs could be substituted if desired with minor modifications to the circuit.

It is seen from the foregoing description of the invention that a novel decade counter circuit is provided exhibiting features of advantage over the prior art devices. Having therefore described the invention and its mode of operation, those features of novelty believed descriptive of the nature and scope of the invention are described with particularity in the appended claims.

What is claimed is:

1. A binary decade counter for producing an output signal at the count of nine, said counter comprising four intercoupled bistable-state flip-flop binary counter stages each having the same preselected state at the beginning of the count, the intercoupling means at least from one stage to one other stage including a cathode impedance tuned to a frequency defining a trigger pulse for the succeeding stage and shunted by a unidirectionally conductive damping device for producing a single output pulse in response to each transition of the respective flip flop to said preselected one of its two bistable states; a source of input signal pulses to be counted; a source of timing pulses; means including a coincidence gate responsive to the concurrence of input signals and timing signals for applying said signal pulses to be counted to the first stage; an output circuit coupled to and jointly controlled by the first and fourth stages for delivering a count-of-nine D.-C. signal in response to the ninth input signal pulse, said output circuit including a coincidence detector circuit for detecting D.-C. level signals at said first and fourth stages landfor, delivering. aQDJC. signal ,when, each saidlfirst and fourthstages is.concurrently in that onefof its t-wo.' .-bistable states (which is opposite from -the said preselected :state, output means responsive to said count-ofrnine'D C.

signal and to the.succeeding timing pulse for developing a count-of-nine. outputpulse at the time. of said succeeding timing pulse; aninhibit circuit coupled wand-controlled by :said output :means for disconnecting the secondkflipfioprstage fromathe. first stage in responseto said counto'f-nine output pulse, thereby to prevent a tenth input signal pulse from passing the first stage; and a clearing circuit coupled to and jointly controlled by both the source of input signal pulses and the output means for clearing the fourth stage in" response to every tenth input-signal pulse, said clearing circuit including a coincidence detector which in response to a count-of-nine output pulse and the tenth input signal pulse delivers a clearing signal to set the fourth state in its said preselected state.

2. Apparatus as claimed in claim 1 characterized by the inclusion of means for developing count-of-nine output pulses of both polarities, and further characterized in that the inhibit circuit is responsive to output pulses of one polarity and the clearing circuit is responsive to output pulses of the other polarity.

3. A binary type decade counter for delivering an output signal at the count of nine, said counter comprising four bistable-state flip flops connected as binary counters, each of said flip flops being comprised of a pair of unidirectionally conductive devices having anode and cathode electrodes; means for initially setting each of said flip flops to a cleared condition in the same preselected state; means for developing output pulse signals from each said first, second and third flip flops in response to the respective flip flop changing to said preselected state from its other state, said means comprising for each said flip flop a cathode load impedance tuned to produce a pulse for triggering the succeeding flip flop and shunted by a unidirectionally conductive damping device; a source of input pulses to be counted; a source of timing pulses;

' means including a coincidence gate responsive to the coincidence of an input pulse and a timing pulse for applying input pulses to be counted to said first flip flop to change its state in response to each pulse so applied; means for applying to said second flip flop output pulse signals developed by said first flip flop across the cathode load impedance of the first flip flop when it changes to said preselected state from its other state thereby to change the state of said second flip flop in response to each pulse signal so applied; means for applying to said third fiip flop output pulse signals developed by said second flip flop across the cathode load impedance of the second flip flop when it changes to said preselected state from its other state thereby to change the state of said third flip flop in response to each pulse signal so applied; means for applying to said fourth flip flop output pulse signals developed by said third flip flop across the cath ode load impedance of the third flip flop when it changes to said preselected state from its other state thereby to change the state of said fourth flip flop in response to each pulse signal so applied; means for deriving a D.-C. output signal from said fourth flip flop when it is in a state opposite to the said preselected state; means for deriving a D.-C. output signal from said first flip flop when it is in a state opposite to the said preselected state; means including an output coincidence gate responsive to the concurrence of said D.-C. output signals derived from said first and fourth flip flops for developing a count-of-nine D.-C. signal in response to the ninth input pulse; means responsive to said count-of-nine D.-C. signal and to the following timing pulse for developing a count-of-nine output pulse at the time of the said following timing pulse; an inhibit gate connected between said first and second flip flops; means for applying said count-of-nine output pulse to said inhibit circuit to inhibit a change of state of said second flip flop when said first fliptflop changesifromtjtspppositetqitstpl eseleeted be in condition.fbr receivingjtli'therjnput P uLIse s to be state in response to .thextenthj iqput'pul sm;a esettipgpo- ,counted.

incidence gate towhieh gaid ingupputses and said-.cqupt- .of-nin'e utput pulses are a'ppliedjor developing a clear- Rfe renc'es Cited in of th is paten t ing-signal for said fourth stage upon coincidenceqf said 5'31; v e i signals so applied to said'resetting gate; and mean'for' f A E K t r 'applying said plearing signal to. said fqm thfiip 'flqp. to f 2,4 3, .Ovr k Sept; 16, 194 change it from its opposite towits said p res e l ected state, '5 1,566,918 Bergfors Sept.'4, '1951 whereby each of said four fliptfiops istcleared to said pre- ,6 ,383 Moody Dec- 7 7 r r selected state at the end of the tenth input pulse, thereby to 10" 2,706,811 7 Steele m. Apr 19, 1955 

